This invention relates to a programmable logic device (PLD) integrated circuit, and more particularly, the invention relates to a high density PLD with great flexibility and high performance using less memory than current PLDs.
The conventional way of constructing a PLD is to employ an AND gate array connected to an OR gate array, with inputs to the AND array. Both AND OR arrays are programmable, in order to provide a desired logical output from the OR array.
The outputs from OR gates can be connected to a functionally configurable macrocell, whereby the OR outputs can be latched, fed back to the AND array, or connected to I/O pins. The OR outputs can also be utilized as inputs to the AND array. The flexibility and capability of the macro cell can be increased by introducing into the cell configurable output-enables, configurable multiple selectors, configurable register clocks, register set and register reset signals.
The recent rapid development of semiconductor technology has made possible the design and manufacture of very complex integrated circuits. As a result, high density PLDs with very high flexibility and performance are commercially available. In these PLDs, in order to maintain high capability, it is more effective to divide AND OR arrays into small logic blocks, and connect them with a global connection facility. Because of the relatively small size of arrays, earlier high density PLDs had only one register permanently connected to every I/O pin. As the scale of arrays increased, the number of I/O pins was limited by package size and could not be increased accordingly. The logic capacity of PLDs was thus limited. Consequently, it is desirable to increase the number of registers with the concomitant increase of array scale, i.e., to increase the registers per I/O pin. This requires circuits that are used to manage the outputs and feedback of increased registers.
The performance of the high density device depends heavily on how the logic blocks are constructed and how they are connected together. Most of today's high density PLD products are constructed of logic blocks and a global interconnection, with all the logic blocks being connected together by the global interconnection, thus allowing information to be communicated between logic blocks. All the outputs from the logic block are fed into the global interconnection and all the inputs to the logic block come from the global interconnection. With more than one register per I/O pin, these PLDs use I/O control block to handle the outputs, where outputs are multipexed. This structure offers very high logic capability and is able to perform complex logic functions. However, three problems emerge with the structure. First with the number of registers per I/O pin increasing, a very complex I/O control block will result in more chip array area being used and low output performance. The global interconnection becomes the bottleneck of device performance with all the feedbacks from the logic blocks inputting into it and all the inputs of logic blocks outputting from it, without any local feedback within logic blocks. Lastly, the controls of the macro cell are fed into the cells in the same way as other logic signals, which also negatively affects the performance of the control signals.